The present invention relates to a semiconductor device, and more particularly to an improved base layer structure covering a contact hole or a via hole formed in an insulation layer in a semiconductor device and a method of forming the same.
In prior art, a semiconductor device with a via hole or a contact hole is formed as follows.
With reference to FIG. 1A, a first inter-layer insulator 3-1 is formed on a silicon substrate 1. A first level interconnection 2 is formed over the first inter-layer insulator 3-1. A second inter-layer insulator 3-2 is formed on the first level interconnection 2. A hole such as a contact hole or a via hole is formed in the second inter-layer insulator 3-2 so that a part of the first level interconnection 2 is shown through the hole. A spontaneous oxide film is removed from the bottom of the hole. An RF sputtering is carried out to edge portions 4 of the hole in the second inter-layer insulator 3-2 so that the edge portions of the hole in the second inter-layer insulator 3-2 are etched to have a curved shape.
With reference to FIG. 1B, a base layer 5 such as a titanium layer or a titanium nitride layer is deposited by a sputtering method onto the surface of the second inter-layer insulator 3-2 and on the bottom and side walls of the hole. An aluminum layer 6 is then deposited by a sputtering method onto the base layer 5 so that the aluminum layer 6 fills the hole and extends over the surface of the second inter-layer insulator 3-2. The sputtering method may be carried out at an increased substrate temperature. It is also possible to carry out an annealing process in a sputter chamber after the sputtering process was carried out.
If the edges of the hole in the second inter-layer insulator were not etched as illustrated in FIG. 2, the upper portion of the hole may be blocked with the metal layer 6 so that a void 8 is formed in the hole.
In order to avoid the above problem, the edge portions of the hole are etched by the sputtering process so that the edge portions of the hole have a curved shape as illustrated in FIG. 3.
Alternatively, it is also effective for avoiding the above problem to form a tapered hole wherein side walls of the hole are tapered toward the bottom so that a diameter of the hole is decreased downwardly.
Further, alternatively, it is also effective for avoiding the above problem to form recessed upper portions 10 of the hole wherein the recessed portions are formed by wet etching the second inter-layer insulator before the hole is formed by a dry etching.
After the metal layer 6 is deposited, then a photo-resist mask is formed by a photo-lithography technique for subsequent patterning process to the metal layer by a dry etching thereby to form a second level interconnection and a contact layer which provides a connection between the first and second level interconnections.
As the requirement for scaling down of the semiconductor device has been on the increase, the reduction in diameter of the hole and the reduction in width of the interconnections are also being required. Under these circumstances, it becomes more difficult to carry out an accurate alignment between the hole and the second level interconnection over the hole when a photo-lithography process is made for the formation of the metal interconnection. If the metal interconnection is displaced from the hole, then a part of the metal layer in the upper portion of the hole is also etched by the dry etching process which have, however, carried out to be intended to pattern the metal interconnection as illustrated in FIG. 1C whereby a cavity 7 is formed in the vicinity of the edge portion with the curved shape of the hole.
Since the width and pitch of the interconnections are made narrow, a complete etching to the metal layer for accurate formation of the interconnections requires an over-etching for a relatively long time. If in this case the metal interconnection is displaced from the hole, then the metal layer in the upper portion of the hole is largely etched by the dry etching process. Even if a third inter-layer insulator is then formed over the second level interconnection 6, it is difficult for the third inter-layer insulator fill the cavity 7 as the cavity 7 is extremely narrow. The existence of the cavity in the vicinity of the edge portion of the hole results in formation of a narrowed upper portion of the contact layer. This narrowed upper portion of the contact layer causes a current concentration which may cause a disconnection of the contact layer.
In the above circumstances, it had been required to develop a novel base layer structure formed in a hole such as a contact hole or a via hole in a semiconductor device is free from the above problems.